On-Chip Networks: Impact on the Performance of NUCA Caches

نویسندگان

  • Alessandro Bardine
  • Manuel Comparetti
  • Pierfrancesco Foglia
  • Giacomo Gabrielli
  • Cosimo Antonio Prete
چکیده

Non Uniform Cache Architectures (NUCA) are a new design paradigm for large last-level on-chip caches and have been introduced to deliver low access latencies in wire-delay dominated environments. Their structure is partitioned into sub-banks and the resulting access latency is a function of the physical position of the requested data. Typically, NUCA caches make use of a switched network to connect the different subbanks and the cache controller. While on-chip networks [2, 3] have been adopted as communication infrastructures in other scenarios, NUCA caches represent an emerging technology and the influence of the network parameters on their performance needs to be investigated. This work analyzes how different parameters for the on-chip network, namely hop latency and buffering capacity of routers, may affect the overall performance of NUCA-based systems for the single processor case, assuming a reference NUCA organization proposed in literature [5, 4]. This analysis shows that the sensitivity of the system to the hop latency is very high, thus suggesting that multi-cycle router architectures [6, 1] are not adequate; moreover, limited buffering capacity is sufficient to achieve a good performance level.

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تاریخ انتشار 2008